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GLOBALFOUNDRIES Details Technology Targeted at 22 nm
| written by Jake - June 16, 2009 20:25 |
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GLOBALFOUNDRIES today described an innovative technology that could overcome one of the key hurdles to advancing high-k metal gate (HKMG) transistors. This would bring the industry one step closer to the next generation of mobile devices with more computing power and vastly improved battery life.
The semiconductor industry is celebrated for overcoming seemingly insurmountable odds to continue the trend toward smaller, faster, and more energy-efficient products. Performed in partnership with IBM through GLOBALFOUNDRIES' participation in the IBM Technology Alliance, the new research is designed to enable the continued scaling of semiconductor components to the 22 nanometer node and beyond. At the 2009 Symposium on VLSI Technology in Kyoto, Japan, GLOBALFOUNDRIES reported the first demonstration of a technique that allows the equivalent oxide thickness (EOT) in a high-k metal gate (HKMG) transistor to scale down to well beyond the level required for the 22nm node, while maintaining a combination of low leakage, low threshold voltages, and superior carrier mobility.  HKMG is a critical component of GLOBALFOUNDRIES' technology roadmap. This development could eventually provide customers with another tool to enhance the performance of their products, particularly in the fast-growing market for ultra-portable notebooks and smartphones with extended battery life. In conjunction with IBM and the alliance partners, we are tapping our global knowledge base to develop advanced technologies that will allow our customers to stay at the leading edge of semiconductor manufacturing. said Gregg Bartlett, senior vice president of technology and research and development.
To maintain the switching precision of a HKMG transistor, the EOT of the high-k oxide layer must be reduced. However, reducing the EOT increases the leakage current, which can contribute to an increase in the power consumption of a microchip. GLOBALFOUNDRIES and IBM have developed a new technique that overcomes this barrier, demonstrating for the first time that EOT scaling to well beyond the 22nm node can be achieved while maintaining the necessary combination of leakage, threshold voltages, and carrier mobility. The results were successfully demonstrated through fabrication of an n-MOSFET device with EOT of 0.55nm and a p-MOSFET with EOT of 0.7nm. |
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