Intel Developing Ultra-Low Power 65 nm Process
"With the number of transistors on some chips exceeding one billion, it is clear that improvements made for individual transistors can multiply into huge benefits for the entire device," said Mark Bohr, director of Intel Process Architecture and Integration. "Test chips made on Intel’s ultra-low power 65nm process technology have shown transistor leakage reduction roughly 1000 times from our standard process. This translates into significant power savings for people who will use devices based on this technology."
Intel’s ultra-low power, 65nm process technology includes several key transistor modifications which enable delivery of low power benefits while providing industry-leading performance. These transistor modifications result in significant reductions in the three major sources of transistor leakage: sub-threshold leakage, junction leakage and gate oxide leakage. The benefits of reduced transistor leakage are lower power and increased battery life.
Intel’s 65nm processes combine higher-performance and lower-power transistors, a second-generation version of Intel’s strained silicon, eight high-speed copper interconnect layers and a low-k dielectric material. Building chips using the 65 nm processes will allow Intel to double the number of transistors it can build on a single chip today (using Intel’s 90nm technology).